A continuing goal of integrated circuit fabrication is to increase integration density. An approach utilized for achieving increased integration density is to reduce the footprint of individual electrical components so that more components can be fit across a unit of semiconductor real estate. For instance, capacitors have become increasingly tall and thin in an effort to reduce the footprint of individual capacitors, while retaining desired levels of capacitance.
A problem that can occur as capacitors become tall and thin is that the tall, thin storage node structures formed during fabrication of the capacitors may tip, or even topple, during a fabrication process. Accordingly, various structures have been developed to provide support to the storage node structures. Example support structures are lattice structures, such as those described in U.S. Pat. No. 6,667,502, and in U.S. Patent Publication Numbers 2005/0051822 and 2005/0054159.
Another problem that may occur during fabrication of tall, thin storage nodes is that spaces between adjacent storage nodes may function as capillaries during an etching process, and/or during a rinsing process, so that solution is drawn into such spaces. Adhesion of the solution with the adjacent storage nodes may pull the adjacent storage nodes into one another, and the storage nodes may then stick to one another. The sticking of the storage nodes to one another may be referred to as stiction.
A prior art capacitor storage node fabrication process is described with reference to FIGS. 1-5 to illustrate the stiction problem.
Referring to prior art FIG. 1, a portion of a semiconductor construction 10 is illustrated. The construction includes a semiconductor base 12. The base 12 may be, for example, a semiconductor wafer, such as a monocrystalline silicon wafer. The base 12, alone or in combination with various materials, may be referred to as a “semiconductive substrate” or “semiconductor substrate.” The terms “semiconductive substrate” and “semiconductor substrate” mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
A pair of electrically conductive nodes 14 and 16 are supported by base 12. The nodes may be, for example, conductively doped regions of the semiconductor wafer and/or pedestals (for instance, metal-containing pedestals).
A plurality of materials 18, 20 and 22 are over base 12, and over nodes 14 and 16. The materials 18, 20 and 22 may be undoped silicon dioxide, doped silicate glass, and silicon nitride, respectively. The doped silicate glass may be, for example, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), etc. The material 20 may be referred to as a support material, in that it ultimately supports capacitor storage nodes (as discussed below), and the material 22 may be referred to as a lattice material in that it ultimately forms a lattice to provide additional support for the capacitor storage nodes.
Referring to FIG. 2, openings 24 and 26 are formed through materials 18, 20 and 22, and to nodes 14 and 16, respectively. The openings may be formed by providing a photolithographically-patterned photoresist mask (not shown) over material 22; transferring a pattern from the photoresist mask to materials 18, 20 and 22 with one or more etches, and then removing the mask to leave the structure shown in FIG. 2.
Referring to FIG. 3, electrically conductive storage node material 28 is formed within openings 24 and 26. The storage node material may comprise titanium nitride. The storage node material may be formed by depositing the storage node material within the openings and over material 22, and then removing the storage node material from over material 22 with chemical-mechanical polishing (CMP). The storage node material forms storage nodes 23 and 25 within openings 24 and 26, respectively.
Referring to FIG. 4, an opening 30 is formed through material 22 to expose the underlying support material 20. Opening 30 may be representative of a plurality of openings formed through material 22 so that all of material 20 may be removed with a subsequent isotropic etch (discussed below with reference to FIG. 5). Opening 30 may be formed by providing a photolithographically-patterned photoresist mask (not shown) over material 22; transferring a pattern from the photoresist mask to material 22 with an etch, and then removing the mask to leave the structure shown in FIG. 4.
Referring to FIG. 5, support material 20 (FIG. 4) is removed with an isotropic etch. It appears that material 22 is floating in the view of FIG. 5, because the only structures shown in FIG. 5 are those within the cross-sectional plane of the figure. Structures out of the plane are not illustrated in order to simplify the drawing. The material 22 is thus not floating at the processing stage of FIG. 5, but instead is supported by regions that are not visible in the cross-section shown in FIG. 5. The supporting regions may be analogous to those shown and described in U.S. Patent Publication No. 2005/0054159.
Support material 20 (FIG. 4) may be removed with an aqueous etchant comprising about 5% (by volume) hydrofluoric acid in water. After the etching of material 20, the etchant may be removed by a rinse with deionized water, and then the deionized water may be removed by drying the construction 10 (i.e., the water may be volatilized from the construction). The drying may be enhanced through utilization of isopropyl alcohol, acetone and/or other azeotropic solvents.
A capillary 31 forms between adjacent storage nodes 23 and 25. Solvent within such capillary during etching, rinsing and/or drying may pull the material 28 of storage node 23 into the material 28 of storage node 25. The material 28 of storage node 23 sticks to the material 28 of storage node 25 through stiction forces, and thus a short is formed and maintained between the two storage nodes 23 and 25.
It would be desirable to develop new methods of patterning capacitors which alleviate or prevent the shorting illustrated in FIG. 5. It would be further desirable for the new methods to have applications beyond fabrication of capacitors.